1. Field of the Invention
The present invention relates to a substrate for a semiconductor element. The semiconductor element is mounted on the substrate. In particular, the present invention relates to a method for manufacturing a substrate which has structural characteristics that are similar to those of a lead frame. The present invention also relates to a semiconductor device using the substrate.
2. Description of the Related Art
Various types of semiconductor elements such as memory, CMOS, CPU, and the like, are manufactured by a wafer process. These semiconductor elements have a terminal for electrical connection. The magnitude of the pitch of the terminal for electrical connection is different from the magnitude of the pitch of the connection part at a print substrate side by approximately several to several hundred times. A semiconductor element is attached to the connection part at the print substrate side. Therefore, when the semiconductor element is about to be connected with the print substrate, an intermediary substrate (a substrate for mounting a semiconductor element) called an “interposer” is used for pitch conversion. The semiconductor element is mounted on one side of this interposer. A connection with the print substrate is made at another surface or a peripheral of the substrate. The interposer includes a metallic lead frame in the interior or at a front surface. An electrical connection channel is routed by the lead frame. In this way, the pitch of an external connection terminal is expanded. The external connection terminal makes a connection with the print substrate.
FIGS. 4A-4C are schematic diagrams showing a structure of an interposer using a QFN (Quad Flat Non-lead) type lead frame, which is an example of a conventional interposer. A flat part 15 of a lead frame is provided at a central part of a lead frame. The lead frame is formed primarily of either aluminum or copper. A semiconductor element 16 is mounted on the flat part 15 of the lead frame. A lead 17 with a wide pitch is placed at an outer peripheral part of the lead frame. A wire bonding method is used to connect the lead 17 and the terminal for electrical connection of the semiconductor element 16. The wire bonding method uses a metal wire 18 such as an Au line and the like. An overall integration is made at a final stage by performing a molding process with a molding resin 19.
When the semiconductor element has a small number of terminals, the connection between the print substrate and the interposer is conducted by attaching a metallic pin on an extraction electrode 20 at an external extension part of the interposer. Furthermore, when the semiconductor element has a large number of terminals, a Ball Grid Array is used. According to the Ball Grid Array, a solder ball is positioned in an array pattern at an external connection terminal at an outer peripheral part of the interposer.
When an area is small and there is a large number of terminals, a wiring layer may be configured to have multiple layers by stacking a plurality of layers. According to this method, it is possible to cope with a large number of terminals. However, the structure of the substrate becomes intricate. Hence, the reliability and stability are reduced. Thus, the above configuration is not suitable for mounting on a vehicle, for example, which requires a high degree of reliability.
Several types of interposers have been designed. The material used to create the interposer and the structure of the interposer are different. For example, an interposer is configured so that ceramic is used in the structure of a portion holding the lead frame part. Another type of interposer is configured so that the base material of the interposer is an organic substance such as P-BGA (Plastic Ball Grid Array), CSP (Chip Size Package), or LGA (Land Grid Array). These interposers are utilized as appropriate according to actual use and required configurations.
In any of these cases, as the size of semiconductor elements become smaller, as the number of pins increases, and/or as the speed of the semiconductor elements increases, adjustments are made by the interposers described above. For example, a fine pitching and an adjustment to high speed signals are made. The fine pitching is made to the connection part connecting with the semiconductor element of the interposer. Taking into consideration that the pitch has become more and more minute, it is necessary that the pitch of a terminal portion of recent interposers be approximately 80 to 120 μm.
Incidentally, the lead frame is used as a conduction part and a supporting component. It is preferable that the thickness of the lead frame be at least 100 μm to 120 μm, so that the etching process may be performed with stability, and so that an appropriate handling is made. Furthermore, a certain magnitude of the land is required to obtain an adequate amount of joint strength during the wire bonding process. Taking these conditions into consideration, it is believed that the pitch of the lead of the lead frame may be minimized to approximately 120 μm, while the width of the lead line may be made finer to approximately 60 μm.
Japanese Unexamined Patent Application, First Publication No. H10-022440, for example, discloses a substrate for a semiconductor element having a similar characteristic as the structure of a lead frame. According to Japanese Unexamined Patent Application, First Publication No. H10-022440, the structure of the substrate is such that a premold resin is a supporting body of a metal wiring. Thus, Japanese Unexamined Patent Application, First Publication No. H10-022440 discloses a method that can solve the problems described above and achieves an even finer pitch of the lead frame.
Hereinafter, a method, disclosed in Japanese Unexamined Patent Application, First Publication No. H10-022440, of manufacturing a substrate for a semiconductor element is described. A resist pattern for creating a connection post is formed on a first surface of a metal plate. A resist pattern for creating a wiring pattern is formed on a second surface. An etching process is performed on a copper to a desired thickness from above the first surface. Thereafter, a premold resin is filled into the first surface. In this way, a resin layer is formed. The thickness of the resin layer is made as thick as possible while the bottom surface of the connection post is exposed with certainty. Next, an etching process is performed on the second surface. Thus, a wiring pattern is formed. The resist patterns at both surfaces are peeled off. In this way, the method is completed.
The substrate for a semiconductor element manufactured as described above has a structure such that metal is supported by a premold resin. Therefore, even though the thickness of the metal is made small to a level at which fine etching is possible, the etching process can be performed with stability.
However, according to the method for manufacturing a substrate for a semiconductor element described in Japanese Unexamined Patent Application, First Publication No. H10-022440, there is a technical difficulty in the step of applying a premold resin to a surface which was etched midway in a thickness direction of the metal plate. This is because the thickness of the application must be thick enough to provide the necessary rigidity to the substrate, while at the same time, the bottom surface of the connection post must be completely exposed.
A concrete solution for an application while controlling the thickness is, for example, a method in which a syringe and the like is used to pour resin into one point of a bottom of an applied surface, and wait until the resin permeates the entire applied surface or an area wide enough to form a resin with an even thickness. Then, the next resin is poured in. This procedure is repeated. However, the premold resin has a certain level of viscosity. Therefore, it takes time for the premold resin to spread. Hence, there is a problem in terms of productivity.
Further, the premold resin may become spherical due to the effects of surface tension of the premold resin. As a result, the premold resin might cluster in a narrow region. In this case, even if the amount of premold resin that was infused is small, the height might become large, thereby causing a faulty condition. For example, the height might reach the bottom surface of the connection post.
Another solution is to use a dispenser and the like. According to this solution, a small amount of resin is placed in succession to a bottom surface of the application.
However, this solution is also problematic in terms of productivity. In addition, the premold resin may become spherical due to the effects of surface tension of the premold resin. As a result, the premold resin might cluster in a narrow region. In this case, even if the amount of premold resin that was infused is small, the height might become large, thereby causing a faulty condition. For example, there may be an obstruction in connectivity due to the premold resin attaching the bottom surface of the connection post.
A solution to this problem is suggested. According to this solution, for example, when the first surface is filled with a premold resin, the first surface is first filled with resin so that the resin covers the first surface in its entirety. Then, the resin is solidified. Thereafter, the first surface is grinded from above. Thus, the connection post is exposed.
In more concrete terms, based on calculation, premold resin is applied on the first surface. The amount of this premold resin is greater than the amount necessary to fill the first surface. When the premold resin is solidified, a film or a plate-like cover is placed over it. The material of the film is such that the film may be easily peeled off. Further, a pressing operation is performed from above it. Resin is filled in even to a minute part of the first surface. Then, the resin is solidified. Next, the cover is removed. A grinding operation is conducted on the premold resin covering the first surface. A buff, for example, is used in the grinding operation. The premold resin is removed until the upper bottom surface of the connection post is exposed.
In this way, it is possible to obtain a premold resin layer, in a relatively easy manner, having enough thickness to support a substrate. At the same time, this premold resin layer may be obtained so that the connection post is exposed with reliability.
However, there are other solutions as well. In other words, when the premold resin is applied to the first surface, in order for the premold resin to permeate the first surface even to minute portions, it is theoretically necessary to have a greater amount of premold resin compared to the required amount. When this is pressed, the excess resin normally spreads out from where the substrate main body pattern is located. Thus, the excess resin spreads out towards an outer side.
Here, in most cases, within the metal plate that becomes an ingredient, the portion which becomes the substrate main body is assigned and located neat a central part of the ingredient. An alignment mark is placed outside the portion which becomes the substrate main body, or in the peripheral part of the ingredient. The alignment mark is used to make an alignment after the substrate is completed, when components such as semiconductor chips and the like are mounted, or when an attachment is made inside a metal molding and a molding operation is performed, and the like.
The amount of resin applied to the first surface should be calculated so that there is no excess portions. However, the portion spreading outside does not become zero. In some cases, the excess portion spreads widely in a particular direction. In this case, when the excess resin reaches the alignment mark, the excess resin covers up the alignment mark. As a result, there is a problem in that subsequent operations are obstructed.
The present invention is made according to the problems described above. Thus, the present invention provides a semiconductor device and a method for manufacturing a substrate for a semiconductor element, which can easily and reliably solve the problem that, during a process in which the substrate for a semiconductor element having a premold resin is manufactured, excess resin spreads to an outer peripheral part of the ingredient and obstructs alignment marks and the like from operating.